This disclosure relates to a technique of recovering read performance degradation of a storage device, and more particularly, to a method of operating a storage device to recover performance degradation due to a retention characteristic and a method of operating a data processing system including the same.
Memory devices that store data may be volatile memory devices or non-volatile memory devices. A flash memory device is an example of electrically erasable programmable read-only memory (EEPROM) in which a plurality of memory cells are erased or programmed in a single program operation.
A program operation and a read operation are performed on each page and an erase operation is performed on each block. Flash memory devices include a memory cell array, which includes a plurality of blocks. Each of the blocks includes a plurality of pages. Each of the pages may include a plurality of non-volatile memory cells, and may include one or more rows of memory cells. Flash memory devices may be divided into NAND-type flash memory devices and NOR-type flash memory devices.
A flash memory cell includes a floating gate. Charges stored in a floating gate (i.e., charges related with information) are lost a long time after the information is stored in the flash memory cell. Accordingly, a distribution characteristic degrades. When retention lasts for a long time without being powered, the threshold voltage of the flash memory cell is changed. When the changed threshold voltage is lower than a read voltage, a value of a bit read from the flash memory cell during a read operation is changed. As a result, information read from the flash memory could be an error bit.
When threshold voltages of at least some of flash memory cells included in a page are changed, page data corresponding to the page may include a lot of error bits, also described as bit errors. When a read operation is performed on these flash memory cells, serious read performance degradation could occur due to excessive execution of an algorithm for recovering error bits and such read performance degradation could last for a long time.
In order to avoid the performance degradation due to flash memory cells on which the algorithm for recovering error bits are excessively performed, data relocation may be performed on the flash memory cells. However, since the performance degradation could get worse during the data relocation, the criteria of data relocation are usually conservative. For instance, when an error bit level of flash memory cells is lower than a certain level, only an algorithm for recovering error bits is performed. In other cases, both an algorithm and data relocation are performed. Once flash memory cells are subjected to data relocation, they are not subjected to the algorithm for recovering error bits any more until their retention begins to deteriorate, and therefore, there is no initial performance degradation.